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Senior Compiler Engineer, Agentic Compiler Systems
We are looking for an outstanding Senior Compiler Engineer to help build the next generation of intelligent compiler technologies for NVIDIA's accelerated computing stack. Our team works at the intersection of compilers, agentic systems, numerical correctness, and verification to create compiler systems that can reason about, generate, optimize, and validate code transformations across software and hardware boundaries. In this role, you will help design and build advanced compiler and verification systems that improve developer productivity, system performance, and confidence in correctness. This includes developing compiler-oriented agents and workflows, building numerical validation and verification infrastructure, and co-designing with NVIDIA's compiler, runtime, library, and hardware teams to bring new capabilities into production tools and products. What you'll be doing: Design, build, and optimize intelligent low-level compiler systems, including compiler-oriented agents, multi-step transformation workflows, tool use, memory, and orchestration. Develop systems that can reason about low-level IR, code generation, optimization passes, scheduling, numerical precision, and performance tradeoffs across GPU-centric workloads. Build the data, environments, verification, reward, and evaluation systems needed to continuously improve compiler quality, numerical correctness, robustness, and performance. Develop infrastructure for numerical validation, differential testing, regression detection, and correctness verification for generated or transformed code. Co-design compiler and verification workflows across NVIDIA's software stack, spanning models and inference, compiler pipelines, runtimes, libraries, kernels, and GPUs. Collaborate closely with internal compiler, CUDA, library, runtime, and hardware teams to integrate new compiler, agentic, and verification capabilities into NVIDIA products. Drive performance analysis and optimization for generated or transformed code, with a strong focus on correctness, scalability, and real-world deployment. What we need to see: Bachelor's degree in Computer Science, Electrical Engineering, Applied Mathematics, or a related field, or equivalent experience; MS or PhD preferred. 5+ years of relevant industry or academic experience in compilers, AI systems, numerical computing, verification, high-performance computing, or related areas. Strong hands-on experience in compiler implementation, program analysis, code generation, optimization, low-level performance engineering, or correctness infrastructure. Experience in one or more of the following areas: agent systems, coding agents, compiler automation, numerical analysis, program verification, differential testing, or formal/semi-formal validation methods. Strong C/C++ and Python programming skills, with solid software engineering fundamentals; experience with Rust is a plus. Experience with GPU programming and performance optimization using CUDA or comparable accelerator platforms. Ability to work effectively across system boundaries, from model-driven workflows and compiler infrastructure to runtime and hardware-aware optimization. Ways to stand out from the crowd: Track record of building high-impact compiler infrastructure, coding agents, verification frameworks, correctness tooling, or developer tools. Deep expertise in low-level compiler stacks such as LLVM, MLIR, PTX, Triton, or other IR/codegen frameworks. Experience building or optimizing AI-assisted compilation, numerical validation systems, equivalence checking, autotuning, or compiler verification workflows. Deep expertise in GPU systems, numerical behavior, and performance optimization, demonstrated through benchmark results, deployed systems, publications, or widely used software. Publications or open-source leadership in compilers, numerical computing, verification, formal methods, agentic AI, high-performance computing, AI systems, or programming systems. With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology industry's most desirable employers. We have some of the most brilliant and hardworking people in the world working with us and our product lines are growing fast in some of the hottest state of the art fields such as Virtual Reality, Artificial Intelligence, Deep Learning and Autonomous Vehicles. Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 152,000 USD – 241,500 USD. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until November 7, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Advanced Compiler Engineer - Quantum Software - 10...
Quantinuum are seeking an Advance Compiler Engineer to join our growing Quantum Software team in Cambridge, UK. In this role, you will help shape the design and implementation of the next generation TKET quantum compiler and contribute to the Guppy quantum programming language. This is a unique opportunity to work at the intersection of software development, compiler design, and quantum computing research. You will collaborate closely with a small, dynamic team throughout the full development lifecycle — from research and design to programming and testing — with the freedom to think independently and make a real impact. Key Responsibilities Maintain and contribute to a Rust-based compiler codebase. Develop and apply optimization methods for quantum-classical programs. Design and implement novel features for quantum programming languages. Collaborate with key stakeholders across research and engineering teams. You Must Have Software development experience, preferably in Rust or Python. Broad knowledge of programming languages, paradigms, and compiler concepts. Ability to work collaboratively, communicate technical ideas clearly, and write clean, maintainable code. Familiarity with collaboration tools (e.g., version control, issue tracking) and development tools (e.g., debugger, profiler, testing frameworks). A 2:1 or higher degree in Computer Science, Mathematics, Engineering, or a related discipline. Ability to read and implement ideas from technical research materials. We Value Experience designing classical compilers and programming languages. Knowledge of quantum computing, quantum algorithms, or programming quantum systems. Experience with compiler frameworks such as LLVM or MLIR. Familiarity with formal methods, type theory, or program verification tools. Background in large software system architecture and design.
MTS, Inference Performance Visibility
About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Join our team and take the lead in illuminating the performance landscape of our cutting-edge ML accelerator. We are seeking a highly skilled engineer to design and develop a sophisticated performance analysis tool, tailored specifically for our hardware. You will be instrumental in creating the essential tooling that enables our ML engineers and customers to understand workload behavior, identify performance bottlenecks, and unlock the full potential of our hardware, accelerating the most demanding ML applications in the world. This is a unique opportunity to shape performance analysis for novel hardware from the ground up. Key responsibilities - Lead the design and architecture of a comprehensive performance analysis suite, including data collection mechanisms, data processing pipelines, analysis engines, and user interfaces (CLI and/or GUI). - Develop robust methods to capture performance data directly from our custom ML accelerator hardware (e.g., hardware performance counters, execution unit status, memory access patterns) via driver interfaces or other mechanisms. - Implement tracing for host-side API calls (runtime libraries, driver interactions) and system-level events (CPU activity, PCIe traffic, memory usage, network contention) related to our workloads. - Design and implement techniques to accurately correlate performance events across the host CPU, device driver, PCIe bus, multiple accelerators, and multiple hosts, ensuring precise time synchronization. - Build analysis modules to automatically interpret collected trace and counter data, identifying key performance limiters (e.g., compute-bound, memory bandwidth-bound, latency-bound, PCIe-bound, specific hardware bottlenecks). - Develop intuitive visualizations (timelines, dependency graphs, resource utilization charts, statistical summaries) to clearly communicate performance characteristics and bottlenecks to users. - Work closely with hardware architects, firmware engineers, driver developers, compiler engineers, and ML application engineers to understand their needs, define tool requirements, and provide expert guidance on performance analysis and optimization using the tool. Representative projects - Architect and implement the core data collection framework for hardware performance counters on a custom PCIe-based accelerator. - Develop a kernel driver module or user-space service for low-overhead tracing of accelerator activity. - Design and build a correlated timeline view visualizing CPU API calls, driver submissions, PCIe transfers, and accelerator execution units. - Create an analysis pass to detect and quantify memory access inefficiencies or PCIe bandwidth saturation while transacting on a PCIe-attached accelerator. You may be a good fit if you have - Strong proficiency in C++ or Rust - Proficiency in Python is a plus - Deep understanding of computer architecture (CPU, GPU, accelerators), memory hierarchies (caches, DRAM), and interconnects (especially PCIe). - Proven experience in low-level performance analysis, profiling, and bottleneck identification on complex hardware systems (GPUs, CPUs, FPGAs, or custom accelerators). - Experience with performance analysis tools (e.g., NVIDIA Nsight, AMD uProf, Intel VTune, perf, Tracy, ETW). - Experience working close to hardware, potentially reading performance counters or interacting directly with device drivers. Strong candidates may also have experience with (Nice-to-have qualifications) - Direct experience developing performance analysis or debugging tools. - Experience with ML accelerator architectures (GPUs, TPUs, etc.). - Experience with kernel-mode driver development (Linux or Windows). - Understanding of compiler internals, code generation, and optimization. - In-depth knowledge of the PCIe protocol and analysis tools (PCIe analyzers). - Experience with multi-chip or multi-host accelerator systems (e.g., TPU pods, or NVidia DGX clusters) - Experience with firmware or embedded systems development. - Experience with hardware description languages (Verilog, VHDL) or hardware verification. Benefits - Medical, dental, and vision packages with generous premium coverage - $500 per month credit for waiving medical benefits - Housing subsidy of $2.5k per month for those living within walking distance of the office - Relocation support for those moving to San Jose (Santana Row) - Various wellness benefits covering fitness, mental health, and more - Daily lunch + dinner in our office - Unlimited compute budget subject to ROI justification How we’re different Etched believes in the Bitter Lesson http://www.incompleteideas.net/IncIdeas/BitterLesson.html. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
Technical Product Manager – Control System
Summary QuEra is looking for Technical Product Manager to coordinate a cross-functional development program for the control system at the heart of our next-generation quantum processor units (QPUs)—which may become the world’s first fault-tolerant quantum computers. This role will bridge multiple technical teams within science and engineering organizations to ensure successful development of a cutting-edge control system capable of supporting high fidelity, low latency real time decision-making at scale on a neutral atom QPU, integrating multiple hardware inputs and outputs (digital, analog, RF, microwave), along with cutting-edge machine learning decoders and calibration routines. The role requires strong leadership and stakeholder management skills, to coordinate between and align diverse technical teams, translating high-level technical roadmaps into actionable requirements and tasks going all the way down to individual subsystems. An ideal candidate will also be effective at organizing and documenting full, traceable hierarchies of requirements for all control system hardware and software, down to the level of individual components and interfaces. Responsibilities - Translate technical roadmaps into actionable plans with clear milestones, owners, dependencies, and risk mitigation strategies - Build full traceable requirement hierarchies from top-level physics goals down to subsystem specifications with input from technical stakeholders - Clearly define and track interfaces between different subsystems: compiler, sequence orchestrator, waveform generation, decoder, calibration - Define and manage requirements for subsystem testing and integration testing with hardware-validated outputs prior to deployment on QPUs - Contribute to developing test procedures and sequences that validate whether subsystem and integration requirements are met - Coordinate priorities and timelines across multiple technical teams: theory, compiler, software engineering, etc. - Support translation of R&D output into product specifications and launch - Maintain clear, structured communication to internal leadership and external stakeholders on development status, risks, and decisions Qualifications - Bachelor's degree in physics, electrical engineering, computer science, or a related technical subject - Deep understanding of electronic instrumentation for control systems relevant to neutral atom quantum computing (e.g. digital, analog, RF, microwave) at both the programming and hardware validation level - Strong ability to communicate and coordinate across diverse scientific and engineering stakeholders - Exceptional organization and documentation skills - Creativity and initiative to solve open-ended technical and organizational problems Preferred Qualifications - PhD in physics, electrical engineering, computer science, or a related subject - Background in relevant subjects such as quantum computing, quantum information science, and atomic, molecular and optical (AMO) physics - At least 2 to 5 years of experience managing execution of complex technical products and / or projects in high tech industries - Experience with low-level programming (e.g., Rust, C++), compiler engineering, and / or related tooling for control systems - Experience with building traceable product requirements and / or systems engineering for hardware-software interfaces - Strong track record of translating emerging research into pragmatic product requirements and developer-ready deliverables What a Successful First Year Looks Like The approximate base salary range for this position is $150,000 - $250,000. We consistently monitor external market data and update base salary ranges accordingly. We determine base compensation decisions on several factors, including as geographic placement, role-specific knowledge, skills, and/or experience. In addition to our base salary offerings, we also provide equity grants for all new hires. QuEra is committed to cultivating a diverse work environment and is proud to be an equal opportunity employer. We highly value diversity in our current and future employees and do not discriminate (including in our hiring and promotion practices) based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.
Software Engineer, Silicon Design Methodology
About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence. You will turn evolving architecture and design needs into reusable tools and workflows that improve iteration speed, quality, and then apply those tools to help construct world-class silicon. You’ll work closely across architecture, design, verification, performance modeling, and systems software. This role is well suited for an engineer who enjoys building high quality software and is motivated by the challenge of improving velocity and quality of the silicon development process. In this role, you will: - Develop and scale design methodologies for rapid first-party chip development and apply them to construct complex custom chips - Create abstractions that allow hardware structures, configurations, experiments, and results to be represented consistently across tools. - Automate high-value engineering workflows and improve their reproducibility, observability, testability, and ease of use. - Partner with architects, RTL designers, verification engineers, compiler engineers, and systems software engineers to gather requirements and then implement solutions. - Use methodology and tooling to identify design risks early, accelerate iteration, and improve confidence in performance and implementation tradeoffs. - Contribute across multiple aspects of software and hardware development as the first-party silicon program and its development methodology evolve. You might thrive in this role if: - You have strong software engineering skills in C++, Python, Rust, or similar systems-oriented languages. - You have experience building engineering infrastructure, developer tools, simulation frameworks, EDA/CAD tooling, compilers, or verification systems. - You understand digital design and computer architecture well enough to translate silicon-development needs into useful software abstractions. - Have experience integrating RTL and IP components into an SoC. - You have designed APIs, object models, or data models for complex systems and care about extensibility, correctness, and usability. - You are comfortable automating multi-stage workflows, building regression systems, and improving reproducibility across teams. - You can reason across architecture, design, verification, performance modeling, and software boundaries. - You enjoy partnering closely with domain experts and turning loosely defined engineering needs into durable tools and methodologies. - You thrive in rapidly evolving environments and can balance immediate program needs with longer-term platform quality. To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement . Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations. To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form . No response will be provided to inquiries unrelated to job posting compliance. We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link . OpenAI Global Applicant Privacy Policy At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.
Senior Compiler Engineer - Rust GPU
Drive Rust GPU compiler pipelines, custom IR frameworks, and JIT systems that let developers write high-performance GPU kernels in idiomatic Rust.
Senior Compiler Engineer – Rust GPU
NVIDIA is dedicated to reinvent accelerated computing. Reinvention requires great technology and amazing people. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is hiring a Senior Compiler Engineer to join our team driving the next generation of GPU systems programming. We are redefining how developers write high-performance GPU software by bringing the safety, expressiveness, and modern tooling of Rust to native GPU and CUDA development. On this team, you will build cutting-edge compiler pipelines, custom intermediate representation (IR) frameworks, and JIT compilation systems that bridge host and device execution—allowing developers to write memory-safe, high-performance GPU kernels in idiomatic Rust. What you’ll be doing: - Develop Rust-to-GPU Compiler Pipelines: Design, implement, and maintain custom compiler backends (such as rustc codegen backends and proc-macros) and Rust-native intermediate representation (IR) frameworks to compile standard Rust directly to high-performance CUDA PTX and machine code. - Build compiler IRs and Optimizers: Work with modern compiler architectures to lower Rust AST and MIR into IRs including MLIR, PTX, and LLVM, including GPU-specific optimizations. - Support complex ahead-of-time, just-in-time, and link time optimization workflows: Build state-of-the-art tooling to support users targeting a broad family of NVIDIA GPUs, host platforms, and feature sets. - Define Safe Parallel Abstractions: Architect innovative compiler-enforced safety models that extend Rust's ownership, borrowing, and lifetime disciplines across the GPU launch boundary—preventing data races and enforcing memory safety during asynchronous GPU execution. - Expose Next-Gen Hardware Features: Implement type-safe, ergonomic device-side abstractions in Rust for low-level GPU hardware primitives, including shared memory, barriers, scoped atomics, Tensor Memory Accelerator (TMA), and warp/cluster-level operations. - Build the future: Supporting today’s accelerated computing applications is not sufficient. We have to build composable building blocks for others around us to build the applications of tomorrow. What we need to see: - Bachelor's, Master's, or Ph.D. in Computer Science, Computer Engineering, a related field, or equivalent experience. - 5+ years of relevant work or research experience in compiler development, language design, or GPU code generation. - Deep expertise in the Rust programming language, including a strong grasp of compiler internals (rustc), Rust MIR, procedural macros, and Rust's borrow-checker/lifetime model. - Hands-on experience with compiler infrastructures, intermediate representations (IRs), and code generation (such as LLVM IR, MLIR, or custom IR systems). - Solid understanding of parallel programming models, GPU architectures, and CUDA programming. - Strong software design skills, including debugging, profiling, and benchmarking compilers and GPU kernels. - Ability to orchestrate agents for product requirement design, architecture, code development, testing, code review, and issue triage. - Ability to work independently, define project goals and scope, and drive complex compiler-engineering efforts from research to production. Ways to stand out from the crowd: - A track record of contributing to the Rust compiler (rustc), Cargo tooling, or open-source Rust-to-GPU projects. - Experience building custom compiler front-ends, AST translators, or JIT engines. - Familiarity with MLIR or other extensible compiler frameworks. - Deep proficiency in low-level GPU programming, including the use of modern hardware features (e.g., Tensor Cores, warp-level shuffles, or asynchronous transfer pipelines). - Experience designing Domain-Specific Languages (DSLs) or tile-based programming abstractions for tensor processing. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for programming languages and systems technology, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 152,000 USD - 241,500 USD. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until July 25, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Senior Machine Learning Applications and Compiler...
We are now looking for a Senior Machine Learning Applications and Compiler Engineer! NVIDIA is seeking engineers to develop algorithms and optimizations for our LPX inference and compiler stack. You will work at the intersection of large-scale systems, compilers, and deep learning, crafting how neural network workloads map onto future NVIDIA platforms. This is your chance to be part of something outstandingly innovative! What you’ll be doing: Build, develop, and maintain high-performance runtime and compiler components, focusing on end-to-end inference optimization. Define and implement mappings of large-scale inference workloads onto NVIDIA’s systems. Extend and integrate with NVIDIA’s SW ecosystem, contributing to libraries, tooling, and interfaces that enable seamless deployment of models across platforms. Benchmark, profile, and monitor key performance and efficiency metrics to ensure the compiler generates efficient mappings of neural network graphs to our inference hardware. Collaborate closely with hardware architects and design teams to feedback software observations, influence future architectures, and codesign features that unlock new performance and efficiency points. Prototype and evaluate new compilation and runtime techniques, including graph transformations, scheduling strategies, and memory/layout optimizations tailored to spatial processors. Publish and present technical work on novel compilation approaches for inference and related spatial accelerators at top tier ML, compiler, and computer architecture venues. What we need to see: MS or PhD in Computer Science, Electrical/Computer Engineering, or related field, or equivalent experience, with 5 years of relevant experience. Strong software engineering background with proficiency in systems level programming (e.g., C/C++ and/or Rust) and solid CS fundamentals in data structures, algorithms, and concurrency. Hands on experience with compiler or runtime development, including IR design, optimization passes, or code generation. Experience with LLVM and/or MLIR, including building custom passes, dialects, or integrations. Familiarity with deep learning frameworks such as TensorFlow and PyTorch, and experience working with portable graph formats such as ONNX. Solid understanding of parallel and heterogeneous compute architectures, such as GPUs, spatial accelerators, or other domain specific processors. Strong analytical and debugging skills, with experience using profiling, tracing, and benchmarking tools to drive performance improvements. Excellent communication and collaboration skills, with the ability to work across hardware, systems, and software teams. Ideal candidates will have direct experience with MLIR based compilers or other multilevel IR stacks, especially in the context of graph based deep learning workloads. Ways to stand out from the crowd: Prior work on spatial or dataflow architectures, including static scheduling, pipeline parallelism, or tensor parallelism at scale. Contributions to opensource ML frameworks, compilers, or runtime systems, particularly in areas related to performance or scalability. Demonstrated research impact, such as publications or presentations at conferences like PLDI, CGO, ASPLOS, ISCA, MICRO, MLSys, NeurIPS, or similar. Experience with large-scale AI distributed inference or training systems, including performance modeling and capacity planning for multi rack deployments. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 135,000 CAD - 185,000 CAD for Level 3, and 170,000 CAD - 220,000 CAD for Level 4. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until March 27, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.
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